Operating modes

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6

Operating modes

There are two modes of operation of the power supply: standby and run mode. However

during RUN mode, there are three input voltage regions: low voltage, normal voltage and

high voltage. A brief definition and description of each of these operating regions is

described below.

6.1

Standby mode

STANDBY mode is defined by the following conditions:



VBAT is within the required voltage range



VBAT_SW may or may not be present



IGN is in the OFF state



PSU_EN is not asserted by the microprocessor

During standby mode, all functions are shutdown except the two standby supplies, VKAM

and VSTBY, and the circuitry monitoring IGN and PSU_EN. During standby mode, current

consumption is minimized. The standby functions are powered from VBAT.

There is no currents drawn from VBAT_SW or any other input except those required to

perform the standby functions. Outputs, other than IGN_ON are disabled, sourcing nor

sinking current.

6.2

Run mode

RUN mode is defined by the following conditions:



VBAT is within the required range



VBAT_SW is within the required range



Either IGN is in the Run state and/or PSU_EN is in the active state

During RUN mode, all functions can be enabled. All functions listed above, with the

exception of the standby functions, are powered by VBAT_SW.

If VBAT is not present, the circuit is fully running with the exception of PSU_EN and the

standby functions (VKAM and VSTBY). In this condition the entry into the RUN MODE can

only be performed by the IGN pin and the circuit is kept running until IGN pin is pulled low.

6.2.1

Entry into RUN mode

RUN mode is entered when at least one of the two signals IGN_SW or PSU_EN goes in the

active state. These two signals may be applied in any order or simultaneously.

When the IGN input is valid, the active low IGN_ON signal is asserted.

The design of VDD5, VDDL and VCORE regulators limits the slew rate of the output

voltages during the start-up as indicated in the electrical characteristic table and ensures

that VDD5 is always greater than VDDL and VCORE.

As indicated in Figure 4, the switching regulator starts first with soft start control or reduced

current limitation. When the VB voltage reaches the VDDL_ENUP threshold all the linear

regulators start with controlled slew-rate. The slew-rate control is done controlling the slew