L9758 datasheet(18/30 Pages) STMICROELECTRONICS

18 / 30 page

Electrical characteristics

L9758

18/30

DocID14273 Rev 5

4.9

VSA, VSB, VSC, VSD tracking linear regulator

Tamb = -40 °C to 125 °C, VBAT= VBAT_SW = 5.5 to 26.5 V, unless otherwise specified.

4.10

RST5 and RSTL reset signals

Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified.

Table 15. VSA, VSB, VSC, VSD tracking linear regulator

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

ΔVTRK

Output voltage

tracking accuracy

1 mA < It1 < 50 mA, 6 V < VBAT_SW < 18 V

1 mA < It1 < 5 0mA, 4 V < VBAT_SW < 6 V

-7

-50

ITRKsh

Current limit

Vtck = 4.75 V

100

CTRK

ESR

Output load capacitor Ceramic or Tantalum

μF

mΩ

Ctckmin

ESRmin

Minimum output

capacitor for stability

Ceramic or Tantalum

μF

RRTRK

Ripple rejection

F= 375 kHz

Vdrop

Dropout voltage

Iload = 50 mA

300

TTSD

Thermal shutdown

Vtck = 4.75 V (current limitation)

165

185

°C

THYST

Thermal hysteresis

Vtck = 4.75 V (current limitation)

°C

ITRK

Load current

Table 16. RST5 reset signals

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

IRST5_H

Reset “high” leakage

current

VRST5 = 5.15 V

-3.0

μA

VRST5_L

Reset “low” output

voltage

VDD5 = 4.5 V Ire = 5 mA

VDD5 = 1.0 V Ire = 1 mA

0.4

VFTH_RST5

Reset threshold

decreasing

ΔVDD5/Δt < 0

4.5

VDD5–

0.2

VRTH_RST5

Reset threshold

increasing

ΔVDD5/Δt > 0

4.5

VDD5–

0.07

VHY_RST5

Reset threshold

hysteresis

-50

tACT_RST5

Reset activation out

of tolerance duration

-15

μs

tDEL_RST5

Reset delay

4.7 kΩ < Rext < 47 kΩ

tERR_RST5

Reset delay accuracy Rext ±1%

-15

+15

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