L9758 datasheet(15/30 Pages) STMICROELECTRONICS

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L9758

Electrical characteristics

4.4

VDD5 linear regulator

Tamb = -40 °C to 125 °C, VBAT = VBAT_SW = 5.5 to 26.5 V, unless otherwise specified.

4.5

VDDL linear regulator

Tamb = -40 °C to 125 °C, VBAT= VBAT_SW = 5.5 to 26.5 V, unless otherwise specified.

Table 10. VDD5 linear regulator

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDD5

Output voltage

5 mA < IDD5 < 1 A VBAT_SW => 5.7 V

5 mA < IDD5 < 800 mA

VBAT_SW = 5.5 V

5 mA < IDD5 < 1 A VBAT_SW  4 V

4.9

3.3

5.1

4.0

IDD5_LIM

Current limit

VDD5 = 4.75 V

1200

2500

CDD5

ESR

Output capacitor

Ceramic or Tantalum

C = 4.7 μF

4.7

100

160

μF

mΩ

RRDD5

Ripple rejection

F = 375 kHz

VDD5_MAX

Maximum overshoot

ΔVB/Δt < 70 V/ms

VBAT_SW = 4V → 8 V

5.5

VDD5/t

Output voltage slew rate

at power-up

5 mA < IDD5 < 1 A VBAT_SW = 13.5 V

V/ms

IDD5

Load current

1000

VDD5lineR

Line regulation

6.0 V < VB < 7 V

-25

+25

VDD5loadR Load regulation

5 mA < IDD5 < 1 A

-25

+25

VDD5-Vddl

Start up

VDD5-Vddl during start up

0.5

3.1

Table 11. VDDL linear regulator

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDDL

Output voltage

5 mA < IDDL < 1 A, VPROG3 = Open

4.0 V < VBAT_SW < 18 V

5 mA <IDDL < 1 A, VPROG3 = Low

4.0 V < VBAT_SW < 18 V

3.23

2.55

3.37

2.65

CDDL

ESR

Output capacitor

Ceramic or Tantalum

4.7

100

160

μF

mΩ

RRDDL

Ripple rejection

F = 375 kHz

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