L9300 datasheet(156/178 Pages) STMICROELECTRONICS

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Figure 67. ADC self-test block diagram

GADG2707170755PS

Digital control loop logic BIST

This check is available on demand selecting the corresponding bit in solenoid CONFIGURATION registers. This

self-test can be activated only if the channel is tristated since the control loop is inhibited during its actuation; logic

BIST is performed on the logic core in charge of calibration of the solenoid a/d data and on the current control

loop. In case the logic BIST fails a warning flag is set in the EXCEPTIONS register, the fault is cleared by reading

the related SPI frame. The actual status of the test is mapped on two bits available in the EXCEPTIONS register,

the test is in idle state as long as the CONFIGURATION bit is at 0.

Calibration data check

Calibration data and analog trimming bits to compensate solenoid a/d errors and internal references are stored in

an internal 8kbit NVM memory; memory data are combined in 256 bit sectors with the following architecture:

•

120 data bits

•

8 CRC bits

•

120 data bits

•

8 CRC bits

At each power-on reset release the logic core downloads these data into local registers; at each download the

data integrity is verified by means of CRC check: in case the CRC check fails, a warning flag is set in the

SERVICE FAULT register (error on analog trim) or Exceptions registers (error on channel calibration or ADC

trimming) while local registers affected by the fault are loaded with a “all 0” default to avoid unpredictable

operation. For debugging purpose, SPI bits are available to mask CRC result and force the usage of NVM

memory data; for analog trimming data, the bit in Service Fault Mask register can be used, while for solenoid

channels two bits are available for each channel in Driver Fault MASK registers. Analog trimming data, used by

internal references, are downloaded only after a power-on reset event; in case CRC error happens and masking

of the fault is used the wrong data are downloaded and cannot be reverted to “all 0” value until next turn-on of the

device. Since mask bits are cleared by RES1 event the microcontroller could lose during operation the information

on actual usage of analog trimming data, so CRC error bit is redunded with information sensitive to Service Fault

Mask settings: in this way it is always possible to understand whether analog trimming data in usage are the

masked one or the downloaded one. A simplified drawing of the masking concept is shown in the next figure,

such a procedure is not implemented on Solenoid NVM data (calibration and ADC trim) since these data are

downloaded each time a change in the configuration settings of solenoid channels is requested, so it is always

possible to refresh solenoid bits and CRC check after a reset event.

L9300

Functional safety

DS12258 - Rev 5

page 156/178

L9300 датащи(PDF) 156 Page - STMicroelectronics