L9300 datasheet(19/178 Pages) STMICROELECTRONICS

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Power supply

8.1

VDD1

8.1.1

VDD1 functional description

VDD1 is a configurable buck regulator with internal high–side MOS and external recirculation diode. The

regulator, depending on the status of the VDD1_SEL pin, can provide two different output voltages: if the pin is

floating, VDD1 selected output voltage is 6.5 V, while if it is connected to GND, the output selected voltage is 5 V.

On VDD1_SEL an internal 500 kΩ pull up resistor is present and the pin is latched at power-up, after internal POR

release, to avoid unwanted changes in VDD1 output voltage during operation. The echo of latched value is

available in the SPI registers.

The switching frequency of the buck PWM is around 470 kHz.

The VDD1 regulator has an inductor’s peak current limitation circuitry, as a protection in case of output short to

GND. When the output stage sensed current is higher than current limitation value, the output, after min duty

cycle has expired, is switched off until next PWM rising edge; should the overcurrent condition still be present, the

regulator is forced to work at minimum duty cycle causing a drop in the output voltage.

The status of the current limitation circuit is internally monitored to detect when the regulator is not able to provide

the target output voltage: in case the circuit is triggered, VDD1 OVER CURRENT flag is set in the SPI registers.

The fault condition may be triggered at low battery as well, even if load current is within the specified range (in this

case, the VDD1 OVER CURRENT bit shall be intended as a generic Out of Regulation diagnostic). Under this

condition, the regulator shall operate at 100% duty cycle to minimize dropout.

The diagnostic is not masked during power-up phase.

VDD1 has an internal thermal protection with a dedicated thermal sensor: in case temperature shutdown

threshold is reached and OVER CURRENT flag is set, all the regulators are turned off and a dedicated diagnostic

bit is set (T_SD_VDD1). Once the sensed temperature decreases below the shutdown threshold (plus a thermal

hysteresis), the powerup sequence is restarted and fault bit can be cleared by SPI reading.

Figure 10. VDD1 regulator circuit

VDD 1

VDD 1_SEL

VROUT

VDD1

Buck

VBATP

Control

loop

VCP

Driver

GADG0707171457PS

L9300

Power supply

DS12258 - Rev 5

page 19/178

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