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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA326 датащи(PDF) 34 Page - STMicroelectronics |
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STA326 датащи(HTML) 34 Page - STMicroelectronics |
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34 / 64 page  Register description STA326 34/64 DocID11531 Rev 9 7.6 Configuration register F (addr 0x05) Setting the IDE bit enables this function, which looks at the input I2S data and clocking and will automatically mute all outputs if the signals are perceived as invalid. Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when input clocking is lost. D7 D6 D5 D4 D3 D2 D1 D0 EAPD PWDN ECLE Reserved BCLE IDE OCFG1 OCFG0 01 0 1 1 1 0 0 Table 39. Output configuration selection Bit R/W RST Name Description 1:0 RW 00 OCFG[1:0] Output configuration selection 00: 2-channel (full-bridge) power, 1-channel DDX® is default Table 40. Output configuration selection OCFG[1:0] Output power configuration 00 2 channel (full-bridge) power, 1 channel DDX®: 1A/1B 1A/1B 2A/2B 2A/2B 01 2 (half-bridge) and 1 (full-bridge) on-board power: 1A 1A binary 2A 1B binary 3A/3B 2A/2B binary 10 Reserved 11 1 channel mono-parallel: 3A 1A/1B 3B 2A/2B Table 41. Invalid input detect mute enable Bit R/W RST Name Description 2 RW 1 IDE Invalid input detect auto-mute enable: 0: disabled 1: enabled Table 42. Binary clock loss detection enable Bit R/W RST Name Description 3 RW 1 BCLE Binary output mode clock loss detection enable 0: disabled 1: enabled Obsolete Product(s) - Obsolete Product(s) |
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