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STA326 датащи(PDF) 28 Page - STMicroelectronics

номер детали STA326
подробное описание детали  2.1-channel high-efficiency digital audio system
PDF  64 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA326 датащи(HTML) 28 Page - STMicroelectronics

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Register description
STA326
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DocID11531 Rev 9
Figure 17. Serial input data timing
Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I2S input channel to its corresponding processing channel.
Table 19. Serial input data timing characteristics (fs = 32 to 192 kHz)
Parameter in Figure 17
Value
BICKI frequency (slave mode)
12.5 MHz max.
BICKI pulse width low (T0) (slave mode)
40 ns min.
BICKI pulse width high (T1) (slave mode)
40 ns min.
BICKI active to LRCKI edge delay (T2)
20 ns min.
BICKI active to LRCKI edge delay (T3)
20 ns min.
SDI valid to BICKI active setup (T4)
20 ns min.
BICKI active to SDI hold time (T5)
20 ns min.
Table 20. Delay serial clock enable
Bit
R/W
RST
Name
Description
5
RW
0
DSCKE
Delay serial clock enable:
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices
Table 21. Channel input mapping
Bit
R/W
RST
Name
Description
6
RW
0
C1IM
0: processing channel 1 receives left I2S input
1: processing channel 1 receives right I2S input
7
RW
1
C2IM
0: processing channel 2 receives left I2S input
1: processing channel 2 receives right I2S input
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