ADS5294IPFPR datasheet(41/82 Pages) TI2

41 / 82 page

ADS5294

www.ti.com

SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

Product Folder Links: ADS5294

Submit Documentation Feedback

Table 6. Summary of Functions Supported by Serial Interface (1)(2)(3)(4) (continued)

ADDR.

(HEX)

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

EN_RAMP

1: Enables a repeating full-scale ramp pattern on the outputs;

0: Normal operation

DUALCUSTOM_PAT

1:Enables mode wherein output toggles between two defined codes;

0: Normal operation

SINGLE_CUSTOM_PAT

1: Enables mode wherein output is a constant specified code;

0: Normal operation

BITS_CUSTOM1<13:12>

2 MSBs for single custom pattern (and for the first code of the dual

custom patterns)

BITS_CUSTOM2<13:12>

2 MSBs for second code of the dual custom patterns

TP_SOFT_SYNC

1: Software sync bit for test patterns on all 8 CHs;

0: No sync. Note: in order to synchronize the digital filters using the

SYNC pin, this bit must be set as 0.

PRBS_TP_EN

1: PRBS test pattern enable bit;

0: PRBS test pattern disabled

PRBS_MODE_2

PRBS 9 bit LFSR (23bit LFSR is default)

PRBS_SEED_FROM_REG

1: Enable PRBS seed to be chosen from register 0x23 and 0x24;

0: Disabled

TP_HARD_SYNC

1: Enable the external SYNC feature for syncing test patterns.

0: Inactive. Note: in order to synchronize the digital filters using the

SYNC pin, this bit must be set as 0.

BITS_CUSTOM1<11:0>

12 lower bits for single custom pattern (and for the first code of the

dual custom pattern).

BITS_CUSTOM2<11:0>

12 lower bits for second code of the dual custom pattern

EN_BITORDER

Enables the bit order output.

0 = byte-wise, 1 = word-wise or bit-wise

BIT_WISE

Selects between byte-wise and bit-wise

1: bit-wise, odd bits come out on one wire and even bits come out on

other wire. D15 must be set to '1' for the bit-wise mode.

0: byte-wise, upper bits on one wire and lower bits on other wire

D15 must be set to '0' for the byte-wise mode.

EN_WORDWISE__BY_CH<7:0>

1: Output format is one sample on one LVDS wire and next sample

on other LVDS wire.

0: Data comes out in 2-wire mode with upper set of bits on one

channel and lower set of bits on the other.

Note: D15 must set to '1' for the word-wise mode.

GLOBAL_EN_FILTER

1: Enables filter blocks - global control;

0: Inactive

EN_CHANNEL_AVG

1: Enables channel averaging mode;

0: Inactive

GAIN_CH1<3:0>

Programmable gain - Channel 1

GAIN_CH2<3:0>

Programmable gain - Channel 2

GAIN_CH3<3:0>

Programmable gain - Channel 3

GAIN_CH4<3:0>

Programmable gain - Channel 4

ADS5294IPFPR датащи(PDF) 41 Page - Texas Instruments

ADS5294IPFPR датащи(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

датащи скачать

ссылки URL