ADS5294IPFPR datasheet(14/82 Pages) TI2

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ADS5294

SLAS776E – NOVEMBER 2011 – REVISED APRIL 2018

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(1)

Bit clock and Frame clock jitter has been included in the Set-up and hold timing.

(2)

Values below correspond to tdelay, NOT tPROG

8.8 LVDS Timing at Different Sampling Frequencies — 2-Wire Interface, 7x-Serialization, Digital

Filter Disabled

See

(1)

ADC CLK Frequency (MSPS)

Set-up Time (tsu), ns

Hold Time (tH), ns

tPROG = (6 / 7) × T + tdelay, ns

(2)

Fs = 1 / T

Data Valid to Zero-

Crossing of LCLKP

(both edges)

Zero-Crossing of LCLKP to

Data Becoming Invalid

(both edges)

tPROG = delay from Input clock zero-cross

rising edge to frame clock zero cross (rising

edge)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

0.34

0.57

0.55

0.8

9.5

0.35

0.64

0.8

1.1

9.5

0.7

0.9

1.2

1.5

9.5

1.3

1.6

1.85

9.5

1.7

2.3

9.5

2.9

3.2

3.5

9.5

6.5

6.7

9.5

(1)

Bit clock and Frame clock jitter has been included in the Set-up and hold timing.

(2)

Values below correspond to tdelay, NOT tPROG

8.9 LVDS Timing at Different Sampling Frequencies — 1-Wire Interface, 14x-Serialization,

Digital Filter Disabled

See

(1)

ADC CLK Frequency (MSPS)

Set-up Time (tsu), ns

Hold Time (tH), ns

tPROG = (5 / 7) × T + tdelay, ns

(2)

Fs = 1 / T

Data Valid to Zero-

Crossing of LCLKP

(both edges)

Zero-Crossing of LCLKP to

Data Becoming Invalid

(both edges)

tPROG = delay from Input clock zero-cross

rising edge to frame clock zero cross (rising

edge)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

0.28

0.48

0.28

0.6

7.5

10.5

0.5

0.68

0.54

0.8

7.5

10.5

0.62

0.8

1.25

7.5

10.5

1.2

1.4

1.6

1.9

7.5

10.5

3.1

3.3

3.5

7.5

10.5

NOTE

The LVDS timing specification is only valid when digital decimation filters are disabled.

When digital filters are enabled, the set-up time decreases as the corresponding hold time

increases as shown in LVDS Timing at Different Sampling Frequencies — 1-Wire

Interface, 14x-Serialization, Decimation by 2 Filter Enabled to LVDS Timing at Different

Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 8 Filter

Enabled . The change on LVDS timing also depends on the internal PLL setting of the

ADS5294. See PLL Operation Versus LVDS Timing for more information.

At the highest sampling frequency, 80-MSPS, and decimation of 2 ( for example: effective

data rate = 560 Mbps in 1-wire mode), the set-up time is reduced by 70 ps, (for example:

set-up time, min = 0.43 ns; hold time, min = 0.54 ns). scenario assumes that the

recommended PLL settings are configured as shown in PLL Operation Versus LVDS

Timing

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