LP85571 datasheet(38/49 Pages) TI2

38 / 49 page

LP8557, LP85571

SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015

www.ti.com

10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.7 V and 5.5 V. This input supply

should be well regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition (start-up or rapid brightness change). The resistance of the input

supply rail should be low enough that the input current transient does not cause drop high enough in the LP8557

supply voltage that can cause false UVLO fault triggering.

If the input supply is located more than a few inches from the LP8557 additional bulk capacitance may be

required in addition to the ceramic bypass capacitors. Depending on device EPROM configuration and usage

case the boost converter is configured to operate optimally with certain input voltage range. Examples are seen

in the Detailed Design Procedure. In uncertain cases, TI recommends contacting a TI sales representative for

confirmation of the compatibility of the use case, EPROM configuration, and input voltage range.

11 Layout

11.1 Layout Guidelines

Figure 50 shows an example layout which applies the required proper layout guidelines to be used as a guide for

laying out the LP8557 circuit.

Table 12. Application Circuit Component List

CURRENT/VOLTAGE

COMPONENT

MANUFACTURER

VALUE

PART NUMBER

SIZE (mm)

RATING, RESISTANCE,

TEMPERATURE

Cyntec

10 µH

PIME051E

5.4 × 5.2 × 1.5

2 A, 0.153

Ω

0603

COUT

Murata

4.7 µF (×2)

GRM188R6YA475KE15D

35 V, X5R

(1.6 × 0.8 × 0.8)

0603

CIN

TDK

10 µF

C1608X5R1A106M080AC

10 V, X5R

(1.6 × 0.8 × 0.8)

SOD-123

Diode

Rohm Semiconductor

Schottky

RB160M-40

VR = 40 V, VF = 0.5 V

(3.5 × 1.6 × 0.8)

The following guidelines apply to both LP8557 and LP8557I.

The LP8557 inductive boost converter sees a high switched voltage at the SW pin, and a step current through

the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference

into nearby nodes due to electric field coupling (I = C × dV/dt). The large step current through the diode and the

output capacitor can cause a large voltage spike at the SW and FB pins due to parasitic inductance in the step

current conducting path (V = L × di/dt). Board layout guidelines are geared towards minimizing this electric field

coupling and conducted noise. Figure 48 highlights these two noise-generating components.

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