LP85571 datasheet(23/49 Pages) TI2

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'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

Data- Data

(8 bits)

R/W

Data transfered, byte +

Ack/NAck

Slave Address

(7 bits)

'1' A

R/W

Direction of the transfer

will change at this point

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Sr - REPEATED START CONDITION

NA - ACKNOWLEDGE (SDA High)

'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

R/W

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Data transfered,

byte + Ack

LP8557, LP85571

www.ti.com

SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015

Programming (continued)

Table 1. Data Read and Write Cycles

ADDRESS MODE

Data Read

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = ‘1’>[Ack]

[Register Data]<Ack or Nack>

… additional reads from subsequent

Data Write

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent

<> Data from master; [] Data from slave

8.5.1.8 Register Read and Write Detail

Figure 36. Register Write Format

Figure 37. Register Read Format

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