STM32WB10CCU5 datasheet(41/110 Pages) STMICROELECTRONICS

41 / 110 page

DS13259 Rev 2

41/110

STM32WB10CC

Functional overview

The backup registers are 32-bit registers used to store 80 bytes of user application data

when VDD power is not present. They are not reset by a system or power reset, or when the

device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:



a 32.768 kHz external crystal (LSE)



an external resonator or oscillator (LSE)



one of the internal low power RC oscillators (LSI1 with typical frequency of 32 kHz or

LSI2)



the high-speed external clock (HSE) divided by 32.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the

LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is

functional in all low-power modes except Shutdown mode.

All RTC events (alarm, wakeup timer, timestamp or tamper) can generate an interrupt and

wakeup the device from the low-power modes.

3.19

Inter-integrated circuit interface (I2C)

The device embeds one I2C. Refer to Table 12 for the features implementation.

The I2C bus interface handles communications between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:



I2C-bus specification and user manual rev. 5 compatibility:

–

Slave and master modes, multimaster capability

–

Standard-mode (Sm), with a bitrate up to 100 kbit/s

–

Fast-mode (Fm), with a bitrate up to 400 kbit/s

–

Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

–

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

–

Programmable setup and hold times

–

Optional clock stretching



System Management Bus (SMBus) specification rev 2.0 compatibility:

–

Hardware PEC (packet error checking) generation and verification with ACK

control

–

Address resolution protocol (ARP) support

–

SMBus alert



Power System Management Protocol (PMBus™) specification rev 1.1 compatibility



Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming. Refer to

Figure 6: Clock tree.



Wakeup from Stop mode on address match



Programmable analog and digital noise filters



1-byte buffer with DMA capability

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