STM32WB10CCU5 datasheet(14/110 Pages) STMICROELECTRONICS

14 / 110 page

Functional overview

STM32WB10CC

14/110

DS13259 Rev 2

3.3

Memories

3.3.1

Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm®

Cortex®-M4 processors. It balances the inherent performance advantage of the Arm®

Cortex®-M4 over Flash memory technologies, which normally require the processor to wait

for the Flash memory at higher frequencies.

To release the processor near 80 DMIPS performance at 64 MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 64 MHz.

3.3.2

Memory protection unit

The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to eight protected areas, which can be divided

up into eight subareas. The protection area sizes are between 32 bytes and the whole

4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code must be

protected against the misbehavior of other tasks. It is usually managed by an RTOS



(real-time operating system). If a program accesses a memory location prohibited by the

MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3.3

Embedded Flash memory

The STM32WB10CC device features 320 Kbytes of embedded Flash memory available for

storing programs and data, as well as some customer keys.

Flexible protections can be configured thanks to option bytes:



Readout protection (RDP) to protect the whole memory. Three levels are available:

–

Level 0: no readout protection

–

Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in SRAM or bootloader is

selected

–

Level 2: chip readout protection: debug features (Cortex®-M4 and Cortex®-M0+

JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG

fuse). This selection is irreversible.

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