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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DLPR410 датащи(PDF) 13 Page - Texas Instruments |
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DLPR410 датащи(HTML) 13 Page - Texas Instruments |
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13 / 53 page  13 DLP650LNIR www.ti.com DLPS136 – NOVEMBER 2018 Product Folder Links: DLP650LNIR Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Applies to LVCMOS pins only. Excludes LVDS pins and test pad pins. (2) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than the specified limit in Recommended Operating Conditions. 6.6 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High level output voltage VCC = 3 V, IOH = – 20 mA 2.4 V VOL Low level output voltage VCC = 3.6 V, IOL = 15 mA 0.4 V IOZ High impedance output current VCC = 3.6 V 10 µA IIL Low level input current VCC = 3.6 V, VI = 0 –60 µA IIH High level input current (1) VCC = 3.6 V, VI = VCC 200 µA ICC Supply current VCC (2) VCC = 3.6 V 650 mA ICCI Supply current VCCI (2) VCCI = 3.6 V 350 mA ICC2 Supply current VCC2 VCC2 = 8.75 V 25 mA ZIN Internal differential termination resistance 95 105 Ω ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω CI Input capacitance(1) f = 1 MHz 10 pF CO Output capacitance(1) f = 1 MHz 10 pF CIM Input capacitance for MBRST[0:15] pins f = 1 MHz 160 210 pF (1) See Figure 7 for timing requirements for LVDS. (2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15,13,11,9,7,5,3,1) and D_AP(15,13,11,9,7,5,3,1). (3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15,13,11,9,7,5,3,1) and D_BP(15,13,11,9,7,5,3,1). 6.7 Timing Requirements Over Recommended Operating Conditions (unless otherwise noted). PARAMETER DESCRIPTION SIGNAL MIN TYP MAX UNIT LVDS(1) tC Clock Cycle Duration for DCLK_A LVDS 2.46 ns tC Clock Cycle Duration for DCLK_B LVDS 2.46 ns tW Pulse Duration for DCLK_A LVDS 1.07 1.23 ns tW Pulse Duration for DCLK_B LVDS 1.07 1.23 ns tSU Setup Time for D_A(15:0) before DCLK_A LVDS 0.35 ns tSU Setup Time for D_A(15:0) before DCLK_B LVDS 0.35 ns tSU Setup Time for SCTRL_A before DCLK_A LVDS 0.35 ns tSU Setup Time for SCTRL_B before DCLK_B LVDS 0.35 ns tH Hold time for D_A(15:0) after DCLK_A LVDS 0.50 ns tH Hold time for D_B(15:0) after DCLK_B LVDS 0.50 ns tH Hold Time for SCTRL_A after DCLK_A LVDS 0.50 ns tH Hold Time for SCTRL_B after DCLK_B LVDS 0.50 ns tSKEW Channel B relative to Channel A(2)(3) LVDS –1.23 1.23 ns |
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