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DLP650LNIR

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DLPS136 – NOVEMBER 2018

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7 Detailed Description

7.1 Overview

Optically, the DLP650LNIR consists of 1,024,000 highly reflective, digitally switchable, micrometer-sized mirrors

(micromirrors), organized in a two-dimensional array of 1280 micromirror columns by 800 micromirror rows. Each

aluminum micromirror is approximately 10.8 microns in size (see the Micromirror Pitch in ) and is switchable

between two discrete angular positions: –12° and 12°. The angular positions are measured relative to a 0° flat

state, which is parallel to the array plane (see Figure 15). The tilt direction is perpendicular to the hinge-axis,

which is positioned diagonally relative to the overall array. The On State landed position is directed toward row 0,

column 0 (upper left) corner of the device package (see the Micromirror Hinge-Axis Orientation in ). In the field of

visual displays, the 1280 × 800 pixel resolution is referred to as WXGA or WXGA-800.

Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a

specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell

contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual

micromirrors changes synchronously with a micromirror clocking pulse, rather than being synchronous with the

CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking

pulse results in the corresponding micromirror switching to a 12° position. Writing a logic 0 into a memory cell

followed by a mirror clocking pulse results in the corresponding micromirror switching to a –12° position.

Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the

CMOS memory. Second, application of a micromirror clocking pulse to all or a portion of the micromirror array

(depending upon the configuration of the system). Micromirror clocking pulses are generated externally by the

DLPA200 device, with application of the pulses being coordinated by the DLPC410 controller.

Around the perimeter of the 1280 by 800 array of micromirrors is a uniform band of border micromirrors. The

border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has

been applied to the device. There are 10 border micromirrors on each side of the 1280 by 800 active array.

Figure 11 shows a DLPC410 and DLP650LNIR chipset block diagram. The DLPC410 and DLPA200 control and

coordinate the data loading and micromirror switching for reliable DLP650LNIR operation. The DLPR410 is the

programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset

components, see Feature Description. For a typical system application using the DLPC410 and chipset

components including a DLP650LNIR DMD, see Figure 21.

7.2 System Functional Block Diagram

Figure 11 shows a simplified system block diagram with the use of the DLPC410 with the following chipset

components:

DLPC410

Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control, and DLPA200

timing and control

DLPR410

[XCF16PFSG48C] serial flash PROM contains startup configuration information (EEPROM)

DLPA200

DMD micromirror driver for the DLP650LNIR DMD

DLP650LNIR Spatial light modulator (DMD)

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