DLP2000 datasheet(9/37 Pages) TI2

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6.6 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

COUT

Output capacitance

f = 1 MHz

(1)

Includes LVCMOS pins only

(2)

LVCMOS input pins do not have pullup or pulldown configurations.

(3)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than 8.75 V.

(4)

When DRC_OEZ = high, the internal reset drivers are tri-stated and IBIAS standby current is 3.8 mA.

(5)

Nominal values are measured with VCC = 1.8 V, VOFFSET = 8.5 V, VBIAS = 16 V, and VRESET = –10 V.

6.7 Timing Requirements

MIN

NOM

MAX

UNIT

Rise time(1)

20% to 80% DCLK

2.5

Fall time(1)

80% to 20% DCLK

2.5

Rise time(2)

20% to 80% DATA(11:0), SCTRL,

LOADB

2.5

Fall time(2)

80% to 20% DATA(11:0), SCTRL,

LOADB

2.5

Cycle time(1)

50% to 50% DCLK

12.5

16.67

Pulse duration(1)

50% to 50% DCLK

Pulse duration low(1)

50% to 50% LOADB

Pulse duration high(1)

50% to 50% DRC_STROBE

tsu

Setup time(1)

DATA(11:0) before rising or falling edge

of DCLK

tsu

Setup time(1)

SCTRL before rising or falling edge of

DCLK

tsu

Setup time(1)

LOADB low before rising edge of DCLK

tsu

Setup time(2)

SAC_BUS low before rising edge of

DCLK

tsu

Setup time(2)

DRC_BUS high before rising edge of

DCLK

tsu

Setup time(1)

DRC_STROBE high before rising edge

of DCLK

Hold time(1)

DATA(11:0) after rising or falling edge of

DCLK

Hold time(1)

SCTRL after rising or falling edge of

DCLK

Hold time(1)

LOADB low after falling edge of DCLK

Hold time(2)

SAC_BUS low after rising edge of DCLK

Hold time(2)

DRC_BUS after rising edge of DCLK

Hold time(1)

DRC_STROBE after rising edge of

DCLK

(1)

Refer to Figure 6-2 and Figure 6-3.

(2)

Refer to Figure 6-4 and Figure 6-5.

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DLP2000

DLPS140B – MARCH 2019 – REVISED MAY 2022

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