7.3 Feature Description

7.3.1 Power Interface

For the DLP2000 DMD, the power management IC is the DLPA1000. This driver contains three regulated DC

supplies for the DMD reset circuitry: VBIAS, VRESET, and VOFFSET.

7.3.2 Control Serial Interface

The control serial interface handles instructions that configure the DMD and control reset operation. DRC_BUS

is the reset control serial bus, DRC_OEZ is the active low, output enable signal for internal reset driver circuitry,

DRC_STROBE rising edge latches in the control signals, and SAC_BUS is the stepped address control serial

bus.

7.3.3 High Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed

DDR transfer and compression techniques to save power and time. The high speed interface is composed of

LVCMOS signal receivers for inputs and a dedicated clock.

7.3.4 Timing

The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. Figure 6-6 shows an equivalent test load circuit for the

output under test. The load capacitance value stated is only for characterization and measurement of AC timing

signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

Timing reference loads are not intended as a precise representation of any particular system environment

or depiction of the actual load presented by a production test. System designers should use IBIS or other

simulation tools to correlate the timing reference load to a system environment. Refer to the Section 8 section.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC2607 controller. See the DLPC2607 controller data sheet or

contact a TI applications engineer.

7.5 Window Characteristics and Optics

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous components and system design parameters.

Optimizing system optical performance and image quality strongly relates to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance depends on compliance with the optical system operating conditions described in the following

sections.

7.5.1.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area

should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate

apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the

projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light

path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other

system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror

tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination

numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.

7.5.1.2 Pupil Match

TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally

centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils can create

objectionable artifacts in the display’s border as well as the active area, which may require additional system

apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.

DLP2000

DLPS140B – MARCH 2019 – REVISED MAY 2022

www.ti.com

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