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DIX9211 датащи(PDF) 12 Page - Texas Instruments |
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DIX9211 датащи(HTML) 12 Page - Texas Instruments |
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12 / 70 page ![]() Audio Serial Port A Audio Serial Port B Digital Interface Receiver (DIR) Digital Interface Transmitter (DIT) TX+ TX- SDINA SDOUTA LRCKA BCKA SDINB SDOUTB LRCKB BCKB CPM CS or A0 CCLK or SCL CDIN or A1 CDOUT or SDA INT RST Host Interface (SPI or I C) 2 and General- Purpose Outputs Master Clock Distribution MCLK RXCKI From RXCKO GPO1 GPO2 GPO3 GPO4 AESOUT RXCKO LOCK RX2+ RX2- RX3+ RX3- RX4+ RX4- RX1+ RX1- BLS SYNC Control and Status Registers DIR C and U Data Buffers DIT C and U Data Buffers TI Device Power VDD18 DGND1 VDD33 DGND2 VIO DGND3 VCC AGND BGND Internally Tied to Substrate Copyright © 2017, Texas Instruments Incorporated 12 DIX4192-Q1 SBFS041A – JULY 2016 – REVISED APRIL 2017 www.ti.com Product Folder Links: DIX4192-Q1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 9.2 Functional Block Diagram 9.3 Feature Description 9.3.1 RESET Operation The DIX4192-Q1 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset low pulse duration must be a minimum of 500 ns in length. The user must not attempt a write or read operation using either the SPI or I2C port for at least 500 μs after the rising edge of RST. See Figure 6 for the reset timing sequence of the DIX4192-Q1. In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the RESET bit function. Upon reset initialization, all functional blocks of the DIX4192-Q1 default to the power-down state, with the exception of the SPI or I2C host interface and the corresponding control registers. The user may then program the DIX4192-Q1 to the desired configuration, and release the desired function blocks from the power-down state using the corresponding bits in control register 0x01. |
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