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DIX9211 датащи(PDF) 21 Page - Texas Instruments

номер детали DIX9211
подробное описание детали  DIX4192-Q1 Integrated Digital Audio Interface Receiver and Transmitter
PDF  70 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
Logo TI2 - Texas Instruments

DIX9211 датащи(HTML) 21 Page - Texas Instruments

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Ch2
.
Ch. 1
Ch. 1
Ch2
.
Ch2
.
Ch. 1
Ch. 1
Ch2
.
BLS
(output)
SY C
N
(output)
CorU daa
t
(output)
Bit 0
Bit 1
Bit 2
Bit 4
¼
Block Start
(Fr me
a
0St rtsHe
a
re)
2
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
10
0
10
1
10
2
10
3
JitterFrequency(Hz)
10
4
10
5
10
6
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
20
100
1k
SinusoidalJitterFrequency(Hz)
10k
100k
5
2
1
500m
200m
100m
50m
20m
10m
5m
2m
1m
THD+N
OutputJitterAmplitude
InputJitterAmplitude
21
DIX4192-Q1
www.ti.com
SBFS041A – JULY 2016 – REVISED APRIL 2017
Product Folder Links: DIX4192-Q1
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Feature Description (continued)
The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock
output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags
may be output at the general-purpose output (GPO) pins, or accessed through the status registers through the
SPI or I2C host interface. Refer to General-Purpose Digital Outputs and Control Registers for additional
information regarding the DIR status functions.
Figure 15. DIR Jitter Attenuation Characteristics
Figure 16. DIR Jitter Tolerance Plot
Figure 17. DIR Channel Status and User Data Serial Output Format Through the GPO Pins



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