DIX9211 datasheet(11/70 Pages) TI2

11 / 70 page

DIX4192-Q1

www.ti.com

SBFS041A – JULY 2016 – REVISED APRIL 2017

Product Folder Links: DIX4192-Q1

Submit Documentation Feedback

9 Detailed Description

9.1 Overview

The DIX4192-Q1 is an integrated digital audio interface receiver and transmitter (DIR and DIT). Two audio serial

ports, Port A and Port B, support input and output interfacing to external data converters, signal processors, and

logic devices. On-chip routing logic provides for flexible interconnection between the four functional blocks. The

audio serial ports and DIT may be operated at sampling rates up to 216 kHz. The DIR is specified for a PLL lock

range that includes sampling rates from 20 kHz to 216 kHz. All function blocks support audio data word lengths

up to 24 bits.

The DIX4192-Q1 requires an external host processor or logic for configuration control. The DIX4192-Q1 includes

a user-selectable serial host interface, which operates as either a 4-wire serial peripheral interface (SPI) port or a

2-wire Philips I2C bus interface. The SPI port operates at bit rates up to 40 MHz. The I2C bus interface may be

operated in standard or fast modes, supporting operation at 100 kbps and 400 kbps, respectively. The SPI and

I2C interfaces provide access to internal control and status registers, as well as the buffers used for the DIR and

DIT channel status and user data.

The digital interface receiver (DIR) includes four differential input line receiver circuits, suitable for balanced or

unbalanced cable interfaces. Interfacing to optical receiver modules and CMOS logic devices is also supported.

The outputs of the line receivers are connected to a 1-of-4 data selector, referred to as the receiver input

multiplexer, which is used to select one of the four line receiver outputs for processing by the DIR core. The

outputs of the line receivers are also connected to a second data selector, the bypass multiplexer, which may be

used to route input data streams to the DIT CMOS output buffer and differential line driver functions. This

configuration provides a bypass signal path for AES3-encoded input data streams.

The DIR core decodes the selected input stream data and separates the audio, channel status, user, validity, and

parity data. Channel status and user data is stored in block-sized buffers, which may be accessed through the

SPI or I2C serial host interface, or routed directly to the general-purpose output pins (GPO1 through GPO4). The

validity and parity bits are processed to determine error status. The DIR core recovers a low jitter master clock,

which may be used to generate word and bit clocks using on-chip or external logic circuitry.

The digital interface transmitter (DIT) encodes digital audio input data into an AES3-formatted output data

stream. Two DIT outputs are provided, including a differential line driver and a CMOS output buffer. Both the line

driver and buffer include 1-of-2 input data selectors, which are used to choose either the output of the DIT AES3

encoder, or the output of the bypass multiplexer. The line driver output is suitable for balanced or unbalanced

cable interfaces, while the CMOS output buffer supports interfacing to optical transmitter modules and external

logic or line drivers. The DIT includes block-sized data buffers for both channel status and user data. These

buffers are accessed through either the SPI or I2C host interface, or may be loaded directly from the DIR channel

status and user data buffers.

The DIX4192-Q1 includes four general-purpose digital outputs, or GPO pins. The GPO pins may be configured

as simple logic outputs, which may be programmed to either a low or high state. Alternatively, the GPO pins may

be connected to one of 13 internal logic nodes, allowing them to serve as functional, status, or interrupt outputs.

The GPO pins provide added utility in applications where hardware access to selected internal logic signals may

be necessary.

Functional Block Diagram shows a simplified functional block diagram for the DIX4192-Q1. Additional details for

each function block will be covered in respective sections of this data sheet.

DIX9211 датащи(PDF) 11 Page - Texas Instruments

DIX9211 датащи(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL