SDA

SCL

Start Condition

S

Stop Condition

P

17

TCA9538

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SCPS199D – AUGUST 2014 – REVISED OCTOBER 2016

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Feature Description (continued)

8.3.3

RESET Input

The RESET input can be asserted to reset the system while keeping the VCC at its operating level. A reset can

be accomplished by holding the RESET pin low for a minimum of tW. The TCA9538 registers and I

2C/SMBus

state machine are changed to their default states once RESET is low (0). Once RESET is high (1), the I/O levels

at the P port can be changed externally or through the master. This input requires a pull-up resistor to VCC if no

active connection is used.

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9538 in a reset condition

until VCC has reached VPORR. At that point, the reset condition is released and the TCA9538 registers and

SMBus/I2C state machine initialize to their default states. After that, VCC must be lowered to below VPORF and

then back up to the operating voltage for a power-on reset cycle.

8.5 Programming

8.5.1 I2C Interface

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 15). After the Start condition, the device address

byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address inputs (A0–A1) of the slave device must

not be changed between the Start and the Stop conditions.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (Start or Stop) (see Figure 16).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 15).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 17). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 15. Definition of Start and Stop Conditions