Data From

Shift Register

Data From

Shift Register

Write Configuration

Pulse

Write Pulse

Read Pulse

Write Polarity

Pulse

Data From

Shift Register

Output Port

Register

Configuration

Register

Input Port

Register

Polarity

Inversion

Register

Polarity

Register Data

Input Port

Register Data

GND

ESD Protection

Diode

P0 to P7

VCC

Output Port

Register Data

Q1

Q2

D

CK

FF

Q

Q

D

CK

FF

Q

Q

D

CK

FF

Q

Q

D

CK

FF

Q

Q

To INT

16

TCA9538

SCPS199D – AUGUST 2014 – REVISED OCTOBER 2016

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Product Folder Links: TCA9538

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Copyright © 2014–2016, Texas Instruments Incorporated

Functional Block Diagram (continued)

At power-on reset, all registers return to default values.

Figure 14. Simplified Schematic of P0 to P7

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input

voltage may be raised above VCC to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In

this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage

applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of any P-port I/O configured as an input. After time tiv, the

signal INT is valid. Resetting the interrupt circuit is achieved when data on the ports is changed back to the

original state or when data is read from the Input Port register. Resetting occurs in the read mode at the

acknowledge (ACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK clock pulse

can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after

resetting is detected and is transmitted as an interrupt on the INT pin.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires pull-up resistor to VCC.