| поискавой системы для электроныых деталей |
|
CDC3RL02BYFPR датащи(PDF) 12 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
CDC3RL02BYFPR датащи(HTML) 12 Page - Texas Instruments |
|
12 / 23 page ![]() 8.2 Typical Application The CDC3RL02 is designed for use in mobile applications as shown in Figure 8-2. In this example, a single low noise TCXO system clock source is buffered to drive a mobile GPS receiver and WLAN transceiver. Each peripheral independently requests an active clock by asserting a single clock request line (CLK_REQ_1 or CLK_REQ_2). When both clock request lines are inactive, the CDC3RL02 enters a low current shutdown mode. In this mode, the LDO output, CLK_OUT_1, and CLK_OUT_2 are pulled to GND and the TCXO is not powered. LDO TCXO CLK TCXO REQ TCXO CLK TCXO REQ GPS WLAN TCXO 1µF 2.2µF Li CLK_REQ_1 CLK_OUT_1 CLK_REQ_2 CLK_OUT_2 GND VBATT VLDO CDC3RL02 MCLK _IN Copyright © 2017, Texas Instruments Incorporated Figure 8-2. Mobile Application When either peripheral requests the clock, the CDC3RL02 enables the LDO and powers the TCXO. The TCXO output (square wave, sine wave, or clipped sine wave) is converted to a square wave and buffered to the requested output. 8.2.1 Design Requirements For the typical application, the user must know the following parameters. Table 8-1. Design Parameters PARAMETER DESCRIPTION EXAMPLE VALUE VBATT Input voltage from battery or power supply 3.7V MCLK_IN Input frequency from a TCXO 26MHz 8.2.2 Detailed Design Procedure The designer must verify that all parameters are within the ranges specified in Recommended Operating Conditions. Each device which receives a clock output from the CDC3RL02 must have the CLK request pin connected to the appropriate CLK_REQ pin on the CDC3RL02. This pin enables the output buffer when a device requests the clock signal. Control of the clock outputs is possible by using a GPIO from a controller to control the CLK_REQ pins. If one of the outputs is unused, then tie the CLK_REQ and CLK_OUT pins to ground. If the user wants a CLK_OUT pin always enabled, tie the paired CLK_REQ pin to an external 1.8V source (not VLDO because the LDO output is not enabled until at least one CLK_REQ pin is high). CDC3RL02 SCHS371H – NOVEMBER 2009 – REVISED OCTOBER 2024 www.ti.com 12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: CDC3RL02 |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |