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CDC3RL02BYFPR датащи(PDF) 6 Page - Texas Instruments

номер детали CDC3RL02BYFPR
подробное описание детали  CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer
PDF  23 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
Logo TI2 - Texas Instruments

CDC3RL02BYFPR датащи(HTML) 6 Page - Texas Instruments

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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCLK_IN SINUSOIDAL SOURCE
VMA
Input amplitude
0.3
1.8
V
Additive phase noise
fIN = 26MHz, VMA = 1.8VPP
1kHz offset
–141
dBc/Hz
10kHz offset
–149
100kHz offset
–152
1MHz offset
–148
fIN = 26MHz, VMA = 0.8VPP
1kHz offset
–139
10kHz offset
–146
100kHz offset
–150
1MHz offset
–146
Additive jitter
fIN = 26MHz, VMA = 1.8VPP, BW = 10MHz to 5MHz
0.41
ps (RMS)
tDS
MCLK_IN to CLK_OUT_1/2
propagation delay
12
ns
DCs
Output duty cycle
fIN = 26MHz, VMA > 1.8VPP
45%
50%
55%
CLK_OUT_N OUTPUTS
tr
20% to 80% rise time
CL = 10pF to 50pF
1
5.2
ns
tf
20% to 80% fall time
CL = 10pF to 50pF
1
5.2
ns
tsk
Channel-to-channel skew
CL = 10pF to 50pF (CL1 = CL2)
–0.5
0.5
ns
VOH
High-level output voltage
IOH = –100μA, reference to VLDO
–0.1
V
IOH = –8mA
1.2
VOL
Low-level output voltage
IOL = 20μA
0.2
V
IOL = 8mA
0.55
CDC3RL02
SCHS371H – NOVEMBER 2009 – REVISED OCTOBER 2024
www.ti.com
6
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: CDC3RL02



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