TVP5146M2IPFPR datasheet(78/109 Pages) TI2

78 / 109 page

TVP5146M2

SLES141H

– JULY 2005 – REVISED FEBRUARY 2012

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Table 2-96. VDP Pixel Alignment Register

Subaddress

C2h-C3h

Default

01Eh

Subaddress

C2h

Pixel alignment [7:0]

C3h

Reserved

Pixel alignment [9:0]

Pixel alignment [9:0]:

These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP controller initiates the

program from one line standard to the next line standard. For example, the previous line of teletext to the next line of closed caption.

This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early enough to

allow the new values to be programmed before the current settings are required.

The default value is 0x1E and has been tested with every standard supported here. A new value is needed only if a custom standard is

in use.

Table 2-97. VDP Line Start Register

Subaddress

D6h

Default

06h

VDP line start [7:0]

VDP line start [7:0]:

Sets the VDP line starting address

This register must be set properly before enabling the line mode registers. VDP processor works only in the VBI region set by this

Table 2-98. VDP Line Stop Register

Subaddress

D7h

Default

1Bh

VDP line stop [7:0]

VDP line stop [7:0]:

Sets the VDP stop line address

Table 2-99. VDP Global Line Mode Register

Subaddress

D8h

Default

FFh

Global line mode [7:0]

Global line mode [7:0]:

VDP processing for multiple lines set by the VDP start line register at subaddress D6h and the VDP stop line register at subaddress

D7h.

Global line mode register has the same bit definitions as the line mode registers (see Table 2-121).

General line mode has priority over the global line mode.

Functional Description

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