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TVP5146M2IPFPR датащи(PDF) 53 Page - Texas Instruments

номер детали TVP5146M2IPFPR
подробное описание детали  NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb Filter, and SCART Support
PDF  109 Pages
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производитель  TI2 [Texas Instruments]
домашняя страница  https://www.ti.com
Logo TI2 - Texas Instruments

TVP5146M2IPFPR датащи(HTML) 53 Page - Texas Instruments

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TVP5146M2
www.ti.com
SLES141H
– JULY 2005 – REVISED FEBRUARY 2012
Table 2-42. Fast-Switch Control Register
Subaddress
28h
Default
CCh
7
6
5
4
3
2
1
0
Mode [2:0]
Reserved
FSS edge
Reserved
Polarity FSS
Mode [2:0]:
000 = CVBS
↔ SCART
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Composite (default)
111 = Component only
FSS edge:
FSS is sampled at the rising or falling edge of the sampling clock
0 = Rising edge
1 = Falling edge (default)
Polarity FSS:
0 = 0: YCbCr/RGB, 1: CVBS (4A) (default)
1 = 0: CVBS (4A), 1: YCbCr/RGB
Table 2-43. Fast-Switch SCART Delay Register
Subaddress
2Ah
Default
00h
7
6
5
4
3
2
1
0
Reserved
FSS delay [4:0]
FSS delay [4:0]:
Adjusts the delay between the FSS and component RGB/YPbPr
0 1111 = 15 pixel delay
0 0001 = 1 pixel delay
0 0000 = 0 delay (default)
1 1111 =
–1 pixel delay
1 0000 =
–26 pixel delay
Table 2-44. SCART Delay Register
Subaddress
2Ch
Default
00h
7
6
5
4
3
2
1
0
Reserved
SCART delay [6:0]
SCART delay [4:0]:
Adjusts delay between the CVBS and component (RGB) video
0 1111 = 15 pixel delay
0 0001 = 1 pixel delay
0 0000 = 0 delay (default)
1 1111 =
–1 pixel delay
1 0000 =
–16 pixel delay
Copyright
© 2005–2012, Texas Instruments Incorporated
Functional Description
53
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Product Folder Link(s): TVP5146M2



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