9 / 75 page  IP1000A LF Preliminary Data Sheet 9/75 July 5, 2005 Copyright © 2005, IC Plus Corp. IP1000A LF-DS-R08 PIN Description (continued) Pin no. Label Type Description PCI address/data bus 2, 3, 4, 6, 7, 9, 69, 70, 71, 72, 73, 76, 77, 79, 83, 84, 85, 86, 88, 90, 93. 95, 113, 114, 115, 116, 117, 118, 123, 124, 126, 127, AD [31:0] I/O PCI Bus Address/Data. Address and data are multiplexed on the AD pins. Bits 0 through 31 carry the lower 32 bits of the physical address during the first clock cycle of a transaction, and carry data during the subsequent clock cycles. EEPROM interface / EXPANSION ROM 27 BECS O Boot ROM Chip Select Note: EESK, EEDI, EEDO are shared with EEPROM 28 EECS O EEPROM Chip Select Test pins 25 TEST I,PU Selection of internal test ( tied to ground for normal mode ) 30 NC I,PU NC Analog Power and Ground 47 AVCCH Power Analog Power 3.3V 39, 44, 53, 58 AVCC Power Analog Power 1.8V. 35, 38, 40, 43, 46, 49, 52, 54, 57 AVSS Ground Analog Ground Digital Power and Ground 11, 20, 26, 29, 66, 74, 91, 99, 111, 121 VCC2 Power Digital I/O Power 3.3V 1, 10, 15, 24, 81, 92, 98, 106, 120 VCC1 Power Digital Core Power 1.8V. 5, 13, 23, 33, 65, 75, 89, 97, 109, 122 VSS2 Ground Digital Ground 8, 12, 19, 64, 78, 87, 94, 110, 119, 128 VSS1 Ground Digital Ground |
|
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
