IP1000A LF
Preliminary Data Sheet
35/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.1.7
FramesCheckSeqErrors
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xCC
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
FramesCheckSeq
Errors
Frame Check Sequence Errors is a count of
received frames that are an integral number of
octets in length and do not pass the FCS check.
This does not include frames received with
frame-too-long, or frame-too-short (runt) errors.
FramesCheck-SeqErrors will wrap around to zero
after reaching 0xFFFF. See IEEE 802.3 Clause
30.3.1.1.6.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
FramesCheckSeqErrors
reaches
a
value
of
0xC000. FramesCheckSeqErrors is enabled by
writing a logic 1 to the StatisticsEnable bit in the
MACCtrl
register,
and
a
logic
0
to
the
FramesCheckSeqErrors
bit
within
the
StatisticsMask register.
R/W
3.2.1.8
FramesLostRxErrors
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xCE
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
FramesLostRx-
Errors
Frames Lost Due to Receive Errors is a count of
the number of frames that should have been
received (the destination address matched the
filter criteria) but experienced a receive FIFO
overrun error (the receive FIFO does not have
enough free space to store the received data).
FramesLostRxErrors only includes overruns that
become apparent to the host system, and does
not include frames that are completely ignored
due to a completely full receive FIFO at the
beginning
of
frame
reception.
FramesLostRxErrors will wrap around to zero
R/W
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