IP1000A LF
Preliminary Data Sheet
31/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.1.1
BcstFramesRcvdOk
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xBC
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
BcstFramesRcvd
Ok
Broadcast Frames Received OK is the count of
the number of frames that are successfully
received with destination address equal to the
broadcast
address
(0xFFFFFFFFFFFF).
Bcst-FramesRcvdOk does not include frames
received with frames too long, FCS, length or
alignment errors, or frames lost due to internal
MAC
sublayer
error
(i.e.
overrun).
BcstFramesRcvdOk will wrap around to zero after
reaching
0xFFFF.
See
IEEE
802.3
Clause
30.3.1.1.22.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
BcstFramesRcvdOk reaches a value of 0xC000.
BcstFramesRcvdOk is enabled by writing a logic 1
to the StatisticsEnable bit in the MACCtrl register,
and a logic 0 to the BcstFramesRcvdOk bit within
the StatisticsMask register.
R/W
3.2.1.2
BcstFramesXmtdOk
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xF6
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
BcstFramesXmtd
Ok
Broadcast Frames Transmitted is the count of the
number
of
frames
that
are
successfully
transmitted
to
the
broadcast
address
(0xFFFFFFFFFFFF). Frames transmitted to other
multicast addresses are excluded from this
statistic. Bcst-FramesXmtdOk will wrap around to
zero after reaching 0xFFFF. See IEEE 802.3
Clause 30.3.1.1.19.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
R/W
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