23 / 75 page
IP1000A LF
Preliminary Data Sheet
23/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.1.1
Control Register (Reg0)
Class............................. PHY Registers
Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers
Register Address .......... 0x0
Default .......................... 0x1140
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
0.5:0
Reserved
RO
Always 0
0.6
Speed Selection
(MSB)
0.6
0.13
1
1
= Reserved
1
0
= 1000Mb/s
0
1
= 100Mb/s
0
0
= 10Mb/s
R/W
1
Update
0.7
Collision Teset
1 = Enable COL signal test
0 = Disable COL signal test
R/W
0
0
0.8
Duplex Mode
1 = Full duplex
0 = Half duplex
R/W
1
Update
0.9
Restart
Auto-NEG
1 = Restart Auto-Negotiation Process
0 = Normal operation
R/W
SC
0
SC
0.10
Isolate
1 = electrically Isolate PHY from MII or GMII
0 = normal operation
R/W
0
0
0.11
Power Down
1 = Power down
0 = Normal operation
R/W
0
0
0.12
Auto-Negotiation
Enable
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
R/W
1
Update
0.13
Speed Selection
(LSB)
0.6
0.13
1
1
= Reserved
1
0
= 1000Mb/s
0
1
= 100Mb/s
0
0
= 10Mb/s
R/W
0
Update
0.14
Loopback
1 = enable loopback mode
0 = disable loopback mode
R/W
0
0
0.15
Software Reset
1 = PHY software reset
0 = normal operation
R/W
SC
0
0 (SC)
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