VS6724 datasheet(42/118 Pages) STMICROELECTRONICS

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Host communication - I²C control interface

VS6724

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read. A read message is terminated by the bus master generating a negative acknowledge

after reading a final byte of data.

A message can only be terminated by the bus master, either by issuing a stop condition, a

repeated start condition or by a negative acknowledge after reading a complete byte during

a read operation.

3.2

Detailed overview of the message format

Figure 27. Detailed overview of message format

The V2W generic message format consists of the following sequence:

Master generates a START condition to signal the start of new message.

Master outputs, MS bit first, a 7-bit device address of the slave the master is trying to

communicate with followed by a R/W bit.

R/W = 0 then the master (transmitter) is writing to the slave (receiver).

R/W = 1 the master (receiver) is reading from the slave (transmitter).

The addressed slave acknowledges the device address.

Data transmitted on the bus

When a write is performed then master outputs 8-bits of data on SDA (MS Bit

first).

When a read is performed then slave outputs 8-bits of data on SDA (MS Bit First).

Data receive acknowledge

When a write is performed slave acknowledges data.

SDA

SCL

MSB

LSB

START

repeated

START

condition

ACK

signal

from

slave

STOP

repeated

Start

condition

Device address

MSB

LSB

(Sr)

7-bit device

address

R/W

(A)

8-bit Data

(Sr)

Data byte from

transmitter

R/W=0 - Master

R/W=1 - Slave

ACK

signal

from

receiver

R/W

Bit

0 - Write

1 - Read

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