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VS6724 датащи(PDF) 35 Page - STMicroelectronics |
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VS6724 датащи(HTML) 35 Page - STMicroelectronics |
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35 / 118 page ![]() VS6724 Functional description 35/118 CSI logical DMA channels The purpose of logical channels is to separate different data flows which are interleaved in the data stream, in the case of the VS6724 this allows the identification of the pipe context used for an image frame. The DMA channel identifier number is directly encoded in the 4- byte CSI embedded sync codes. The receiver can then monitor the DMA channel identifier and de-multiplex the interleaved video streams to their appropriate DMA channel. The bChannelID register can have the value 0 to 6. The DMA channel identifier must be fully programmable to allow the host to configure which DMA channels the different video data stream use. ● Logical channel control The channel identifier is a part of CSI synchronization code, upper four bits of last byte of synchronization code. Figure 20. CSI frame structure (VGA example) illustrates the synchronization code with logical channel identifiers. Figure 20. CSI frame structure (VGA example) 2.10.4 VSYNC and HSYNC The VS6724 can provide two programmable hardware synchronization signals: VSYNC and HSYNC. The position of these signals within the output frame can be programmed by the user or an automatic setting can be used where the signals track the active video portion of the output frame regardless of its size. Horizontal synchronization signal (HSYNC) The HSYNC signal is controlled by the bHSyncSetup register. The following options are available: ● enable/disable ● select polarity ● all lines or active lines only ● manual or automatic F F 000 0 DC LC DMA Channel Number Valid channels = 0 to 6 Line code 0x0 = Line Start 0x1 = Line End 0x2 = Frame Start 0x3 = Frame End 32-bit embedded ITU-CSI sync code |
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