VS6724 datasheet(25/118 Pages) STMICROELECTRONICS

25 / 118 page

VS6724

Functional description

25/118

Power Down/Up: The power down state is entered when CE is pulled low or the supplies

are removed.

During the power-down state (CE = logic 0)

●

The internal digital supply of the VS6724 is shut down by an internal switch

mechanism. This method allows a very low power-down current value.

●

The device input / outputs are fail-safe, and consequently can be considered high

impedance.

During the power-up sequence (CE = logic 1)

●

The digital supplies must be on and stable.

●

The internal digital supply of the VS6724 is enabled by an internal switch mechanism.

●

All internal registers are reset to default values by an internal power on reset cell.

Figure 11. Power up sequence

STANDBY mode: The VS6724 enters STANDBY mode when the CE pin on the device is

pulled HIGH. Power consumption is very low, most clocks inside the device are switched off.

In this state I²C communication is possible when CLK is present and when the

microprocessor is enabled.

All registers are reset to their default values. The device I/O pins have a very high-

impedance.

Uninitialised = RAW: The initialize mode is defined as supplies present, the CE signal is

logic 1 and the microcontroller clock has been activated.

During initialize mode the device firmware may be patched. This state is provided as an

intermediary configuration state and is not central to regular operation of the device.

The analogue video block is powered down, leading to a lower global consumption

CLK

AVDD (2.8V)

VDD (1.8V/2.8V)

SDA

SCL

t1 >= 0 ns

t2 >= 0 ns

t3 >= 0 ns

t4 >= 200 µs

Constraints:

low level command(0xC003): enable clocks

setup commands

t5 >= 7 ms (based on 12 MHz external clock frequency, delay is inversely proportional to

standby

POWER DOWN

uninitialised mode

external clock. Max delay for 6 MHz = 14 ms.)

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