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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VS6724 датащи(PDF) 33 Page - STMicroelectronics |
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VS6724 датащи(HTML) 33 Page - STMicroelectronics |
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33 / 118 page  VS6724 Functional description 33/118 Prevention of false synchronization codes The VS6724 is able to prevent the output of 0xFF and/or 0x00 data from being misinterpreted by a host system as the start of synchronization data. This function is controlled the bCodeCheckEnable register. 2.10.2 Mode 1 (ITU656 compatible) The structure of an image frame with ITU656 codes is shown in Figure 18. Figure 18. ITU656 frame structure with even codes The synchronization codes for odd and even frames are listed in Table 3 and Table 4. By default all frames output from the VS6724 are EVEN. It is possible to set all frames to be ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in the Dither control register bank. Table 3. ITU656 embedded synchronization code definition (even frames) Name Description 4-byte sequence SAV Line start - active FF 00 00 80 EAV Line end - active FF 00 00 9D SAV (blanking) Line start - blanking FF 00 00 AB EAV (blanking) Line end - blanking FF 00 00 B6 EAV SAV Frame of image data Line 1 Line 480 Frame blanking period 9D 80 EAV B6 SAV AB |
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