LP5520TLSLASHNOPB datasheet(23/45 Pages) TI2

23 / 45 page

ack from slave

msb Chip Address lsb

ack from slave

msb Register Add lsb

msb

DATA

lsb

stop

ack from slave

noack from master

repeated start

data from slave

start

Id = 20h or 21h

w ack

addr = 05h

ack

r ack Address 05h - data 08h

ack stop

msb Chip Address lsb

Id = 20h or 21h

start

SCL

SDA

start

msb Chip Address lsb

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

SCL

SDA

start

Id = 20h or 21H

ack

addr = 00h

ack

address 00h ± data 41h

stop

ADR6

Bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C SLAVE address (chip address)

LP5520

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SNVS440B – MAY 2007 – REVISED MARCH 2016

Product Folder Links: LP5520

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Programming (continued)

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LP5520 address is 20h when SI=0 and 21h when SI=1. For the

eighth bit, a 0 indicates a WRITE and a 1 indicates a READ. The second byte selects the register to which the

data is written. The third byte contains data to write to the selected register.

Figure 26. I2C Chip Address

w = write (SDA = 0)

r = read (SDA = 1)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address, 20h when SI=0 and 21h when SI=1 for LP5520.

Figure 27. I2C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the I2C Read Cycle waveform.

Figure 28. I2C Read Cycle

7.5.1.2 SPI Interface

The LP5520 is compatible with SPI serial-bus specification, and it operates as a slave. The transmission consists

of 16-bit write and read cycles. One cycle consists of 7 address bits, 1 read/write (RW) bit, and 8 data bits. RW-

bit high state defines a write cycle and low defines a read cycle. SO output is normally in high-impedance state,

and it is active only when data is sent out during a read cycle. The address and data are transmitted MSB first.

The slave select signal (SS) must be low during the cycle transmission. SS resets the interface when high, and it

must be taken high between successive cycles. Data is clocked in on the rising edge of the SCK clock signal,

while data is clocked out on the falling edge of SCK.

LP5520TL/NOPB датащи(PDF) 23 Page - Texas Instruments

LP5520TL/NOPB датащи(HTML) 23 Page - Texas Instruments

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