SX28ACSLASHDP datasheet(34/51 Pages) PARALLAX

34 / 51 page

Parallax SX20AC/SX28AC

www.parallax.com

Page 34 of 51

Rev 1.6 11/20/2006

15.12.2.

Pop Operation

When a return instruction is executed the subroutine stack

is popped. Specifically, the contents of Stack 1 are copied

into the program counter and the contents of each stack

level are moved to the next higher level. For example,

Stack 1 receives the contents of Stack 2, etc., until Stack 7

is overwritten with the contents of Stack 8. Stack 8 is left

unchanged, so the contents of Stack 8 are duplicated in

Stack 7.

15.13. Comparison and Conditional Branch

Instructions

The instruction set includes instructions such as

DECSZ fr (decrement file register and skip if zero),

INCSZ fr (increment file register and skip if zero),

SNB bit (bit test file register and skip if bit clear), and

SB bit (bit test file register and skip if bit set). These

instructions will cause the next instruction to be skipped if

the tested condition is true. If a skip instruction is

immediately followed by a PAGE or BANK instruction

(and the tested condition is true) then two instructions are

skipped and the operation consumes three cycles. This is

useful for conditional branching to another page where a

PAGE instruction precedes a JMP. If several PAGE and

BANK instructions immediately follow a skip instruction

then they are all skipped plus the next instruction and a

cycle is consumed for each.

15.14. Logical Instruction

The instruction set contain a full complement of the

logical instructions (AND, OR, Exclusive OR), with the

W register and a selected memory location (using either

direct or indirect addressing) serving as the two operands.

15.15. Shift and Rotate Instructions

The instruction set includes instructions for left or right

rotate-through-carry.

15.16. Complement and SWAP

The device can perform one’s complement operation on

the file register (fr) and W register. The MOV W,<>fr

instruction performs nibble-swap on the fr and puts the

value into the W register.

Table 15-1: Key to Abbreviations and Symbols

Symbol

Description

Symbol

Description

Working register

Numerical value bit in opcode

File register (memory mapped in range of 00h to FFh)

Bit position selector bit in opcode

Lower eight bits of program counter (file register 02h)

File register / bit selector separator in assembly instruct.

STATUS

STATUS register (file register 03h)

Immediate literal designator in assembly instruction

FSR

File Select Register (file register 04h)

lit

Literal value in assembly language instruction

Carry bit in STATUS register (Bit 0)

addr8

8-bit address in assembly language instruction

Digit Carry bit in STATUS register (Bit 1)

addr9

9-bit address in assembly language instruction

Zero bit in STATUS register (Bit 2)

addr12

12-bit address in assembly language instruction

Power Down bit in STATUS register (Bit 3)

Logical 1’s complement

Watchdog Timeout bit in STATUS register (Bit 4)

Logical OR

PA2:PA0

Page select bits in STATUS register (Bits7:5)

Logical exclusive OR

OPTION

OPTION register (not memory mapped)

Logical AND

WDT

Watchdog Timer register (not memory-mapped)

Swap high and low nibbles (4-bit segments)

MODE

MODE register (not memory mapped)

Rotate left through carry bit

Port control register pointer (RA, RB, RC)

Rotate right through carry bit

Non-memory-mapped register designator

Cecrement file register

File register address bit in opcode

Increment file register

Constant value bit in opcode

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