SX28ACSLASHDP datasheet(29/51 Pages) PARALLAX

29 / 51 page

Parallax SX20AC/SX28AC

www.parallax.com

Page 29 of 51

Rev 1.6 11/20/2006

Figure 12-3 shows the on-chip Power-On Reset sequence

where the MCLR pin is tied to VDD via a 10K resistor.

Note: connecting the MCLR pin directly to the VDD

supply is not recommended. If the VDD signal is stable

before the DRT timeout period expires, the device will

receive a proper reset. However, Figure 12-4 depicts a

situation where VDD rises too slowly. In this scenario, the

DRT will time-out prior to VDD reaching a valid operating

voltage level (VDD min). This means the device will come

out of reset and start operating with the supply voltage not

at a valid level. In this situation, it is recommended that

you use the external RC circuit shown in Figure 12-5. The

RC delay should exceed the time period it takes VDD to

reach a valid operating voltage.

Figure 12-3: Time-Out Sequence on Power-Up

(MCLR not tied to Vdd): Fast Vdd Rise Time

Figure 12-4: Time-Out Sequence on Power-Up

(MCLR not tied to Vdd): Slow Vdd Rise Time

Figure 12-5: External Power-On Reset Circuit

(For Slow Vdd Power-Up)

A 2-bit field in the FUSEX register can be used to specify

the Delay Reset Timer (DRT) timeout period that results

in an automatic wake-up from the power down mode.

10 = 0.25 msec

11 = 18 msec (default)

00 = 60 msec

01 = 1 sec

Note 1: The external Power-On Reset circuit is required

only if VDD power-up is too slow. The diode D helps

discharge the capacitor quickly when VDD powers down.

Note 2: R < 40 kΩ is recommended to make sure that

voltage drop across R does not violate the device

electrical specifications.

Note 3: R1 = 100 Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor C. This helps

prevent MCLR pin breakdown due to Electrostatic

Discharge (ESD) or Electrical Overstress (EOS).

13.0 BROWN-OUT DETECTOR

The on-chip brown-out detection circuitry resets the

device when VDD dips below the specified brown-out

voltage. The device is held in reset as long as VDD stays

below the brown-out voltage. The device will come out of

reset when VDD rises above the brown-out voltage. The

brown-out level is preset to approximately 4.2 V at the

factory. The brown-out circuit can be disabled through

BOR0 and BOR1 bits contained in the FUSEX Word

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