SX28ACSLASHDP datasheet(31/51 Pages) PARALLAX

31 / 51 page

Parallax SX20AC/SX28AC

www.parallax.com

Page 31 of 51

Rev 1.6 11/20/2006

15.0 INSTRUCTION SET

As mentioned earlier, the SX family of devices uses a

modified Harvard architecture with memory-mapped

input/output. The device also has a RISC type architecture

in that there are 43 single-word basic instructions. The

instruction set contains byte-oriented file register,

bitoriented file register, and literal/control instructions.

Working register W is one of the CPU registers, which

serves as a pseudo accumulator. It is a pseudo

accumulator in a sense that it holds the second operand,

receives the literal in the immediate type instructions, and

also can be program-selected as the destination register.

The bank of 31 file registers can also serve as the primary

accumulators, but they represent the first operand and

may be program-selected as the destination registers.

15.1. Instruction Set Features

• All single-word (12-bit) instructions for compact

code efficiency.

• All instructions are single cycle except the jump

type instructions (JMP, CALL) and failed test

instructions (DECSZ fr, INCSZ fr, SB bit, SNB bit),

which are two cycle.

• A set of File registers can be addressed directly or

indirectly, and serve as accumulators to provide first

operand; W register provides the second operand.

• Many instructions include a destination bit which

selects either the register file or the accumulator as

the destination for the result.

• Bit manipulation instructions (Set, Clear, Test and

Skip if Set, Test and Skip if Clear).

• STATUS Word register memory-mapped as a

digit carry, zero, power down, and timeout).

• Program Counter (PC) memory-mapped as register

file allows W to be used as offset register for

indirect addressing of program memory.

• Indirect addressing data pointer FSR (file select

• IREAD instruction allows reading the instruction

from the program memory addressed by W and

upper four bits of MODE register.

• Eight-level, 11-bit push/pop hardware stack for

subroutine linkage using the Call and Return

instructions.

• Six addressing modes provide great flexibility.

15.2. Instruction Execution

An instruction goes through a four-stage pipeline to be

executed (Figure 15-1). The first instruction is fetched

from the program memory on the first clock cycle. On the

second clock cycle, the first instruction is decoded and the

second instruction is fetched. On the third clock cycle, the

first instruction is executed, the second instruction is

decoded, and the third instruction is fetched. On the

fourth clock cycle, the first instruction’s results are

written to its destination, the second instruction is

executed, the third instruction is decoded, and the fourth

instruction is fetched. Once the pipeline is full,

instructions are executed at the rate of one per clock

cycle.

Instructions that directly affect the contents of the

program counter (such as jumps and calls) require that the

pipeline be cleared and subsequently refilled. Therefore,

these instruction take more than one clock cycle.

The instruction execution time is derived by dividing the

oscillator frequency by either one (turbo mode) or four

(non-turbo mode). The divide-by factor is selected

through the FUSE Word register.

Figure 15-1: Pipeline and Clock Scheme

15.3. Addressing Modes

The device supports the following addressing modes:

• Data Direct

• Data Indirect

• Immediate

• Program Direct

• Program Indirect

• Relative

Both direct and indirect addressing modes are available.

The INDF register, though physically not implemented, is

used in conjunction with the indirect data pointer (FSR) to

perform indirect addressing. An instruction using INDF as

its operand field actually performs the operation on the

processing two multiple-byte operands requires alternate

loading of the operand addresses into the FSR pointer as

the multiple byte data fields are processed. Examples:

Direct addressing:

mov

RA,#01

;move “1” to RA

Indirect Addressing:

mov

FSR,#RA ;FSR = address of RA

mov

INDF,#$01

;move “1” to RA

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