1

Arm Cortex-M33 Processor Datasheet

Datasheet

Overview

The Arm Cortex-M33 processor is the first Armv8-M processor designed to address

embedded and IoT markets especially those that require efficient security or digital signal

control. Armv8-M introduces TrustZone which forms the foundation of security for embedded

and IoT applications. The processor has specific features to increase processing at the endpoint

such as a 20% increase in performance over the Cortex-M4, a Digital Signal Processing (DSP)

extension, a Floating-point Unit (FPU), a coprocessor interface to offload compute intensive

operations, and Arm Custom Instructions (ACI) to speed up specific operations.

Features

Feature

Description

Pipeline

3-stage

Software security

Optional TrustZone for Armv8-M, with optional security

attribution unit (SAU) of up to 8 regions

Stack limit checking

DSP extension

Optional DSP/SIMD instructions

Single-cycle 16/32-bit MAC

Single-cycle dual 16-bit MAC

8/16-bit SIMD arithmetic

FPU

Optional single-precision FPU

IEEE 754 compliant

Coprocessor interface

Optional dedicated coprocessor bus interface for up to 8

coprocessor units for custom compute

Arm Custom

Instructions

Custom data path to add custom instructions

Memory protection

Optional Memory Protection Unit (MPU) with up to 16 regions

per security state

Interrupts

Non-maskable Interrupt (NMI) and up to 480 physical interrupts

with 8 to 256 priority levels

Wake-up Interrupt

Controller (WIC)

Optional for waking up the processor from state retention pow-

er gating or when all clocks are stopped

Sleep modes

Integrated wait for event (WFE) and wait for interrupt (WFI)

instructions with Sleep On Exit functionality

Debug

Optional JTAG and Serial Wire Debug ports

Up to 8 Breakpoints and 4 Watchpoints

Trace

Optional Embedded Trace Macrocell (ETM), Micro Trace Buffer

(MTB), Data Watchpoint and Trace (DWT) and Instrumentation

Trace Macrocell (ITM)

Figure 1: Block diagram of

the Cortex-M33 processor