6

ATB Interfaces - The ATB interfaces output trace data for debugging.

The ATB interfaces are compatible with the CoreSight architecture. See the

Arm CoreSight Architecture Specification v3.0 for more information. The instruction

ATB interface is used by the optional ETM, and the instrumentation ATB interface

is used by the optional ITM.

Micro Trace Buffer Interfaces - The MTB AHB slave interface and SRAM interface

are for the optional CoreSight Micro Trace Buffer.

Coprocessor Interface - The coprocessor interface is designed for closely coupled

external accelerator hardware.

Debug AHB Interface - The D-AHB slave interface allows a debugger access to registers,

memory, and peripherals. The D-AHB interface provides debug access to the processor

and the complete memory map.

Cross Trigger Interface - The processor includes an optional CTI Unit that has an

interface that is suitable for connection to external CoreSight components using a

Cross Trigger Matrix (CTM).

Power Control Interface - The processor optionally supports a number of internal power

domains which can be enabled and disabled using Q-channel interfaces connected to a

Power Management Unit (PMU) in the system.

Arm Custom instructions

Arm introduces two sets of three classes of instruction extension in the coprocessor

instruction space:

Three classes operate on the general-purpose register file, including the condition

code flags NZCV

Three classes operate on the floating-point/SIMD register file only

The three classes are defined by the following instruction patterns:

The destination register or the destination register pair of an instruction might be read,

as well as written (non-accumulator and accumulator variants)

The operation code can be split between a true operation code in the custom datapath

and an immediate value used in the custom datapath

Immediate consequences of the above are:

– No operations on the floating-point registers can set condition codes

– There are no operations using registers from both register files

Operations on the general-purpose register file operate on 32-bit registers, or a

dual-register consisting of a 64-bit value constructed from an even-numbered,

general-purpose register and its immediately following odd pair