5

ETM

The optional Embedded Trace Macrocell provides instruction-only capabilities when configured.

See the Arm CoreSight ETM-M33 Technical Reference Manual for more information.

Micro Trace Buffer

The MTB provides a simple low-cost execution trace solution for the Cortex-M33 processor.

Trace is written to an SRAM interface, and can be extracted using a dedicated AHB slave

interface (M- AHB) on the processor. The MTB can be controlled by memory mapped registers

in the PPB region or by events generated by the DWT or through the CTI. See the

Arm CoreSight MTB-M33 Technical Reference Manual for more information.

Debug and Trace

Debug and trace components include a configurable Breakpoint Unit (BPU) for implementing

breakpoints, and a configurable DWT unit for implementing watchpoints, data tracing,

and system profiling.

Other debug and trace components include optional ITM for support of printf() style

debugging, using instrumentation trace. Interfaces are suitable for:

Passing on-chip data through a Trace Port Interface Unit (TPIU) to a Trace Port Analyzer

(TPA), including Serial Wire Output (SWO) mode

A ROM table to allow debuggers to determine which components are implemented

in the Cortex-M33 processor

Debugger access to all memory and registers in the system, including access

to memory-mapped devices, access to internal core registers when the core is halted,

and access to debug control registers even when reset is asserted

Interfaces

The processor has various external interfaces.

Code and System AHB Interfaces - Harvard AHB bus architecture supporting

exclusive transactions and security state.

System AHB Interface - The S-AHB interface is used for any instruction fetch

and data access to the memory-mapped SRAM, peripheral, external RAM

and external device, or vendor_SYS regions of the Armv8-M memory map.

Code AHB Interface - The C-AHB interface is used for any instruction fetch

and data access to the code region of the Armv8-M memory map.

External Private Peripheral Bus - The EPPB APB interface enables access

to CoreSight- compatible debug and trace components in a system connected

to the processor.

Secure Attribution Interface - The processor has an interface that connects

to an external Implementation Defined Attribution Unit (IDAU), which enables

your system to set security attributes based on address.