7

Instruction

Assembly

Inputs

Outputs

General-purpose registers and NZCV flags

CX1{A}

CX1{A}

Pn,{Rd,}Rd,#imm

Immediate and 1x 32-bit GPR/NZCV {same as output}

1x 32-bit GPR or NZCV

CX2{A}

CX2{A}

Pn,{Rd,}Rd,Rn,#imm

Immediate and 2x 32-bit GPR/NZCV {one same as output}

1x 32-bit GPR or NZCV

CX3{A}

CX3{A}

Pn,{Rd,}Rd,Rn,Rm,#imm

Immediate and 3x 32-bit GPR/NZCV {one same as output}

1x 32-bit GPR or NZCV

CX1D{A}

CX1D{A}

Pn,{Rd,}Rd,#imm

Immediate and 1x 32-bit GPR/NZCV {two same as output}

2x 32-bit GPR

CX2D{A}

CX2D{A}

Pn,{Rd,}Rd,Rn,#imm

Immediate and 2x 32-bit GPR/NZCV {two same as output}

2x 32-bit GPR

CX3D{A}

CX3D{A}

Pn,{Rd,}Rd,Rn,Rm,#imm

Immediate and 3x 32-bit GPR/NZCV {two same as output}

2x 32-bit GPR

Vector registers

VCX1{A}.F

VCX1{A}

.F Pn,{Sd,}Sd,#imm

Immediate and 1x 32-bit fp32 register {same as output}

1x 32-bit fp32 register

VCX2{A}.F

VCX2{A}

.F Pn,{Sd,}Sd,Sd,#imm

Immediate and 2x 32-bit fp32 register {one same as output}

1x 32-bit fp32 register

VCX3{A}.F

VCX3{A}

.F Pn,{Sd,}Sd,Sn,Sm,#imm Immediate and 3x 32-bit fp32 register {one same as output}

1x 32-bit fp32 register

VCX1{A}.D

VCX1{A}

.D Pn,{Dd,}Dd,#imm

Immediate and 1x 64-bit fp64 register {same as output}

1x 64-bit fp64 register

VCX2{A}.D

VCX2{A}

.D Pn,{Dd,}Dd,Dn,#imm

Immediate and 2x 64-bit fp64 register {one same as output}

1x 64-bit fp64 register

VCX3{A}.D

VCX3{A}

.D Pn,{Dd,}Dd,Dn,Dm,#imm Immediate and 3x 64-bit fp64 register {one same as output}

1x 64-bit fp64 register

VCX1{A}.Q

VCX1{A}

.Q Pn,{Qd,}Qd,#imm

Immediate and 1x 128-bit vector register {same as output}

1x 128-bit vector register

VCX2{A}.Q

VCX2{A}

.Q Pn,{Qd,}Qd,Qn,#imm

Immediate and 2x 128-bit vector register {one same as output}

1x 128-bit vector register

VCX3{A}.Q

VCX3{A}

.Q Pn,{Qd,}Qd,Qn,Qm,#imm Immediate and 3x 128-bit vector register {one same as output}

1x 128-bit vector register

Pn

Coprocessor number

Sd

Destination register (32-bit vector register)

A

Accumulate

Sn, Sm

Input registers (32-bit vector registers)

Rd

Destination register

Dd

Destination register (64-bit vector register)

Rn, Rm

Input registers

Dn, Dm

Input registers (64-bit vector registers)

{ }

Optional

Qd

Destination register (128-bit vector)

#imm

Immediate value

Qn, Qm

Input registers (128-bit vector registers)

Cortex-M33 Pipeline

3-stage pipeline

Early termination of operation completing in DX

Limited dual issue capability

Five x 16-bit instruction queue

Full Harvard memory interface

Figure 3: Cortex-M33

processor pipeline