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TMP86FS28DFG датащи(PDF) 211 Page - Toshiba Semiconductor |
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TMP86FS28DFG датащи(HTML) 211 Page - Toshiba Semiconductor |
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211 / 272 page ![]() Page 199 TMP86FS28DFG The smaller the external resistor value, the higher the segment/common drive capability, but power con- sumption is increased. Conversely, the larger the external resistor value, the lower the segment/common drive capability, but power consumption is reduced. If the drive capability is insufficient, the LCD may not be displayed clearly. Therefore, select an optimum resistor value for the LCD panel to be used. Figure 16-4 Connection Examples When Using an External Resistor Divider (LCDCR<BRES> = “0”) 16.3 LCD Display Operation 16.3.1 Display data setting Display data is stored to the display data area (assigned to address 0FC0H to 0FD3H, 20bytes) in the DBR. The display data which are stored in the display data area is automatically read out and sent to the LCD driver by the hardware. The LCD driver generates the segment signal and common signal according to the display data and driving method. Therefore, display patterns can be changed by only over writing the contents of dis- play data area by the program. Table 16-5 shows the correspondence between the display data area and SEG/ COM pins. LCD light when display data is “1” and turn off when “0”. According to the driving method of LCD, the number of pixels which can be driven becomes different, and the number of bits in the display data area which is used to store display data also becomes different. Therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the addresses not connected to LCD can be used to store general user process data (see Table 16-4). Note:The display data memory contents become unstable when the power supply is turned on; therefore, the dis- play data memory should be initialized by an initiation routine. Table 16-4 Driving Method and Bit for Display Data Driving methods Bit 7/3 Bit 6/2 Bit 5/1 Bit 4/0 1/4 Duty COM3 COM2 COM1 COM0 1/3 Duty – COM2 COM1 COM0 1/2 Duty – – COM1 COM0 Static – – – COM0 Adjustment of contrast Adjustment of contrast Adjustment of contrast R3 R2 R1 Open V3 V2 C0 C1 V1 VDD VSS Open 1/3 Bias (R1 = R2 = R3) R2 R1 Open V3 V2 C0 C1 V1 VDD VSS Open R1 Open V3 V2 C0 C1 V1 VDD VSS Open Static Keep the following conditon. VDD V3 V2 V1 VSS 1/2 Bias (R1 = R2) |
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