TMP86FS28DFG datasheet(135/272 Pages) TOSHIBA

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Page 123

TMP86FS28DFG

9.3.5 16-Bit Timer Mode (TC3 and 4)

In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad-

able to form a 16-bit timer.

When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the

timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.

After being cleared, the up-counter continues counting. Program the lower byte and upper byte in this order in

the timer register. (Programming only the upper or lower byte should not be attempted.)

Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.

Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the

shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately

after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected

operation may not be obtained.

Note 3: j = 3, 4

Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4)

Table 9-6 Source Clock for 16-Bit Timer Mode

Source Clock

Resolution

Maximum Time Setting

NORMAL1/2, IDLE1/2 mode

SLOW1/2,

SLEEP1/2

mode

fc = 16 MHz

fs = 32.768 kHz

fc = 16 MHz

fs = 32.768 kHz

DV7CK = 0

DV7CK = 1

fc/211

fs/23

128

µs244.14 µs

8.39 s

16 s

fc/27

–8

µs

–

524.3 ms

–

fc/25

–2

µs

–

131.1 ms

–

fc/23

–

500 ns

–

32.8 ms

–

Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later

(fc = 16.0 MHz)

LDW

(TTREG3), 927CH

: Sets the timer register (300 ms

÷27/fc = 927CH).

SET

(EIRE). 5

: Enables INTTC4 interrupt.

(TC3CR), 13H

:Sets the operating clock to fc/27, and 16-bit timer mode

(lower byte).

(TC4CR), 04H

: Sets the 16-bit timer mode (upper byte).

(TC4CR), 0CH

: Starts the timer.

mn-1 mn 0

mn-1 mn

Internal

source clock

Counter

Match

detect

Counter

clear

Match

detect

Counter

clear

TC4CR<TC4S>

TTREG3

(Lower byte)

INTTC4 interrupt request

TTREG4

(Upper byte)

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