TMPR3927 datasheet(3/512 Pages) TOSHIBA

3 / 512 page

Table of Contents

Handling precautions

1. Outline and Features................................................................................................................................................1-1

1.1

Outline ............................................................................................................................................................1-1

1.2

Notation Used in This Manual........................................................................................................................1-2

1.2.1

Numerical Notation................................................................................................................................1-2

1.2.2

Data Notation .........................................................................................................................................1-2

1.2.3

Signal Notation ......................................................................................................................................1-2

1.2.4

Register Notation ...................................................................................................................................1-2

1.3

Features...........................................................................................................................................................1-3

2. Structure

...............................................................................................................................................................2-1

2.1

Block Diagram................................................................................................................................................2-1

3. Pins

...............................................................................................................................................................3-1

3.1

Pinout..............................................................................................................................................................3-1

3.2

Pin Description ...............................................................................................................................................3-3

3.3

Pin Multiplexing .............................................................................................................................................3-9

3.4

Initial Setting Signals....................................................................................................................................3-12

4. Address Mapping ....................................................................................................................................................4-1

4.1

Memory Mapping ...........................................................................................................................................4-1

4.2

Register Mapping ...........................................................................................................................................4-3

5. Configuration ..........................................................................................................................................................5-1

5.1

Chip Configuration Register (CCFG) 0xFFFE_E000 ....................................................................................5-1

5.1.1

Chip Revision ID Register (CRIR) 0xFFFE_E004................................................................................5-3

5.1.2

Pin Configuration Register (PCFG) 0xFFFE_E008...............................................................................5-4

5.1.3

Timeout Error Address Register (TEAR) 0xFFFE_E00C .....................................................................5-7

6. Clocks

...............................................................................................................................................................6-1

6.1

Clock Generator..............................................................................................................................................6-1

6.2

System Control Clock (SYSCLK)..................................................................................................................6-1

6.3

Power-Down Mode.........................................................................................................................................6-2

6.3.1

Operation ...............................................................................................................................................6-2

6.3.2

Register ..................................................................................................................................................6-3

7. Bus Operation..........................................................................................................................................................7-1

7.1

Bus Mastership ...............................................................................................................................................7-1

7.1.1

Snoop Function ......................................................................................................................................7-1

7.1.2

Relationship Between the Endian Mode and Data Bus..........................................................................7-1

7.2

Bus Operation .................................................................................................................................................7-3

7.2.1

Bus Error................................................................................................................................................7-4

8. SDRAM Controller .................................................................................................................................................8-1

8.1

Features...........................................................................................................................................................8-1

8.2

SDRAM Block Diagram.................................................................................................................................8-3

8.3

Memory Configuration ...................................................................................................................................8-4

8.4

Registers .........................................................................................................................................................8-5

8.4.1

Register Mapping...................................................................................................................................8-5

8.4.2

SDRAM Channel Control Registers (SDCCR0-SDCCR7) 0xFFFE_8000 (ch.0)

0xFFFE_8004 (ch.1) 0xFFFE_8008 (ch.2) 0xFFFE_800C (ch.3) 0xFFFE_8010 (ch.4)

0xFFFE_8014 (ch.5) 0xFFFE_8018 (ch.6) 0xFFFE_801C (ch.7).......................................................8-6

8.4.3

SDRAM Timing Register 1 (for SDRAM/SGRAM) (SDCTR1) 0xFFFE_8020...................................8-8

8.4.4

SDRAM Timing Register 2 (for DIMM Flash Memory ) (SDCTR2) 0xFFFE_8024 .........................8-10

8.4.5

SDRAM Timing Register 3 (for SMROM) (SDCTR3) 0xFFFE_8028 ...............................................8-11

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