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TMPR3927 датащи(PDF) 49 Page - Toshiba Semiconductor |
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TMPR3927 датащи(HTML) 49 Page - Toshiba Semiconductor |
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49 / 512 page ![]() Chapter 3 Pins 3-3 3.2 Pin Description Signal Name I/O Description System interface SYSCLK O System Clock Outputs a system clock in full speed mode (at one half the frequency of the TX39/H2 core) or half speed mode (at one quarter the frequency of the TX39/H2 core). The mode depends on the settings of boot signals CHANHS* (ADDR[15] pin) and BME[1:0] (ADDR[9:8] pins). Half speed mode is selected when CHANHS* is set to “0” or BME[1:0] are set to “10”. DATA [31:0] I/O Data Data bus signals. In 16-bit bus mode, the DATA[15:0] pins are used. The pins are equipped with internal pull-up resistors. ACK* I/O Acknowledge In external ACK* mode, this pin is used for an input signal for terminating bus operation. It can also be used as an RDY input (which can be set on a per channel basis). In internal ACK* mode, the pin is used to output a signal for notifying external devices of the termination of bus operation. The pin is equipped with an internal pull-up resistor. RESET* I Reset Initializes the TX3927. The RESET* signal must remain low for at least 512 CPU clock cycles to initialize the internal circuitry. The pin is equipped with an internal pull-up resistor. Clock signals XIN I Crystal Input Connect a crystal resonator or directly input an external clock signal. The clock frequency must match the multiplier specified with boot signals PLLM[1:0] (ADDT[3:2] pins). PLLM[1:0] = “01”: The multiplier is 2. In this case, input an external clock signal, leaving XOUT open. PLLM[1:0] = “11”: The multiplier is 16. In this case, connect a crystal resonator or input an external clock signal. PLLM[1:0] should not be set to “00” or “10”. XOUT O Crystal Output Connect a crystal resonator. This pin must be left open when PLLM[1:0] = “01”. CLKEN I Clock Enable Enables the internal clock generator of the TX3927. The CLKEN signal must remain low until the clock signal input from XIN (a crystal resonator or external clock input) becomes stable as the voltage settles. The pin is equipped with an internal pull-up resistor. |
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