TMPR3927 datasheet(97/512 Pages) TOSHIBA

97 / 512 page

Chapter 8 SDRAM Controller

8-13

8.4.7

SGRAM Load Mask Register (SDCSMRS1) 0xFFFE_8030

R/W

: Type

0x0000

: Initial value

R/W

: Type

0x0000

: Initial value

Bits

Mnemonic

Field Name

Description

31 : 0

SDCSMRS1

SGRAM Load

Mask

SGRAM Load Mask Register 1 (initial value: 0x0000_0000)

A write to this register loads the SGRAM mask register with 32-bit data. The mask

bit(s) for the target channel(s) must be enabled in the command register and the

corresponding control register(s) must be set with a memory type of SGRAM. To

enable the mask bits, perform a NOP command so the external SGRAM is not

affected by an inadvertent command. In the same way as with a command

operation, the write starts only when the SDRAMC is idle. This register always

reads as 0.

Figure 8.4.6 SGRAM Load Mask Register

8.4.8

SGRAM Load Color Register (SDCSMRS2)

0xFFFE_8034

R/W

: Type

0x0000

: Initial value

R/W

: Type

0x0000

: Initial value

Bits

Mnemonic

Field Name

Description

31 : 0

SDCSMRS2

SGRAM Load

Color

SGRAM Load Color Register 2 (initial value: 0x0000_0000)

A write to this register loads the SGRAM color register with 32-bit data. The mask

bit(s) for the target channel(s) must be enabled in the command register and the

corresponding control register(s) must be set with a memory type of SGRAM. To

enable the mask bits, perform a NOP command so the external SGRAM is not

affected by an inadvertent command. In the same way as with a command

operation, the write starts only when the SDRAMC is idle. This register always

reads as 0.

Figure 8.4.7 SGRAM Load Color Register

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