WM8741 datasheet(32/63 Pages) WOLFSON

32 / 63 page

WM8741

Product Preview

PP Rev 1.3 October 2007

ADDRESS

BITS

LABEL

DEFAULT

DESCRIPTION

[4:0]

LAT[4:0]

00 (0dB)

LSBs of attenuation data for left channel in 0.125dB steps. See

Table 25 for details.

DACLLSB

Attenuation

00h

UPDATE

Attenuation data load control for left channel.

0 = Store LAT[4:0] value but don’t update

1 = Store LAT[4:0] and update attenuation on registers 0-3

[4:0]

LAT[9:5]

00 (0dB)

MSBs of attenuation data for left channel in 4dB steps. See Table

25 for details.

DACLMSB

Attenuation

01h

UPDATE

Attenuation data load control for left channel.

0 = Store LAT[9:5] value but don’t update

1 = Store LAT[9:5] and update attenuation on registers 0-3

[4:0]

RAT[4:0]

00 (0dB)

LSBs of attenuation data for right channel in 0.125dB steps. See

Table 25 for details.

DACRLSB

Attenuation

02h

UPDATE

Attenuation data load control for right channel.

0 = Store RAT[4:0] value but don’t update

1 = Store RAT[4:0] and update attenuation on registers 0-3

[4:0]

RAT[9:5]

00 (0dB)

MSBs of attenuation data for right channel in 4dB step. See Table

25 for details.

DACRMSB

Attenuation

03h

UPDATE

Attenuation data load control for right channel.

0 = Store RAT[9:5] value but don’t update

1 = Store RAT[9:5] and update attenuation on registers 0-3

Table 24 Attenuation Control

Note:

The UPDATE bit is not latched. If UPDATE=0, the attenuation value will be written to the pre-latch but not applied to

the relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next

input sample.

DAC OUTPUT ATTENUATION

Registers LAT[9:0] and RAT[9:0] control the left and right channel attenuation. Table 25 shows how

the attenuation levels are configured by the 10-bit words.

L/RAT[9:0]

ATTENUATION LEVEL

000(hex)

0dB

001(hex)

-0.125dB

3FE(hex)

-127.75dB

3FF(hex)

∞dB (mute)

Table 25 Attenuation Control Levels

ATTENUATION CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and

right channel DACs from the next audio input sample. No update to the attenuation registers is

required for ATC to take effect. Right channels register settings are preserved regardless of the

status of ATC.

BIT

LABEL

DEFAULT

DESCRIPTION

Volume Control

04h

ATC

Attenuator Control Mode:

0 = Right channels use Right

attenuation

1 = Right Channels use Left

Attenuation

Table 26 Attenuator Control Mode

WM8741 датащи(PDF) 32 Page - Wolfson Microelectronics plc

WM8741 датащи(HTML) 32 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

датащи скачать

ссылки URL