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WM8741 датащи(PDF) 25 Page - Wolfson Microelectronics plc |
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WM8741 датащи(HTML) 25 Page - Wolfson Microelectronics plc |
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25 / 63 page ![]() Product Preview WM8741 w PP Rev 1.3 October 2007 25 DSP MODE A In DSP mode A, the first bit is sampled on the BCLK rising edge following the one that detects a low to high transition on LRCLK. No BCLK edges are allowed between the data words. The word order is DIN left, DIN right. Figure 17 DSP Mode A Timing Diagram DSP MODE B In DSP mode B, the first bit is sampled on the BCLK rising edge, which detects a low to high transition on LRCLK. No BCLK edges are allowed between the data words. The word order is DIN left, DIN right. Figure 18 DSP Mode B Timing Diagram PCM MODE SAMPLING RATES The WM8741 supports master clock rates of 128fs to 768fs, where fs is the audio sampling frequency (LRCLK), typically 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz or 192kHz. The WM8741 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate. The master clock should be synchronised with LRCLK, although the WM8741 is tolerant of phase differences or jitter on this clock. |
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