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PCAL9722 датащи(PDF) 46 Page - NXP Semiconductors

номер детали PCAL9722
подробное описание детали  Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and reset
PDF  63 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCAL9722 датащи(HTML) 46 Page - NXP Semiconductors

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NXP Semiconductors
PCAL9722
Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and
reset
13 Dynamic characteristics
Over recommended operating free air temperature range, unless otherwise specified. See Figure 29.
VDD(SPI) ≤ 1.65
VDD(SPI) ≤ 5.5
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
fSCLK
maximum input clock frequency
-
2
-
5
MHz
tLOW
LOW period of the SCLK clock
250
-
100
-
ns
tHIGH
HIGH period of the SCLK clock
250
-
100
-
ns
tDS
SDIN to SCLK set-up time
20
-
20
-
ns
tDH
SDIN to SCLK hold time
30
-
30
-
ns
tCSS
CSn to SCLK rise set-up time
100
-
100
-
ns
tCS_HI
minimum CSn de-asserted HIGH
time
200
-
200
-
ns
tCSH
SCLK fall to CSn de-asserted hold
time
20
-
20
-
ns
tDIS(SDOUT) SDOUT disable time
CL = 100 pF
-
150
-
150
ns
tV(SDOUT)
SDOUT valid time
CL = 100 pF
-
200
-
200
ns
Table 66. SPI bus interface timing requirements
SCLK
tLOW tHIGH
1 / fSCLK
tCSS
CS
tDS tDH
D23
D22
D21
SDIN
D2
D1
D0
tCSH tCS_HI
D23
SDOUT
aaa-015956
tV(SDOUT)
tDIS(SDOUT)
Figure 28. Definition of timing
Over recommended operating free air temperature range, unless otherwise specified. See Figure 31.
SPI bus
Symbol
Parameter
Conditions
Min
Max
Unit
tw(rst)
reset pulse width
150
-
ns
trec(rst)
reset recovery time
500
-
ns
trst
reset time
[1]
600
-
ns
Table 67. Reset timing requirements
[1]
Minimum time for SDOUT to become HIGH.
PCAL9722
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 1.1 — 1 May 2023
46 / 63



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